About the Course

This module provides a strong foundation in Verilog design principles and CMOS technology. Students learn Verilog syntax, hierarchy, modeling styles, and the IP design flow from specification to verification and integration. The module also covers SoC-level challenges such as clock/reset domains, CDC/RDC handling, and low-power strategies. Alongside, it introduces the operation of NMOS/PMOS transistors, CMOS logic gate design, and their role in building combinational and sequential circuits, bridging device-level concepts with system-level VLSI design.

📊

Beginner
Level

🕐

90
Minutes

अ

English