About the Course

This module is designed to equip a student with comprehensive knowledge and hands-on skills in the domain of VLSI design flow using open-source EDA tools. It provides a solid theoretical foundation in digital design methodologies and offers in-depth practical exposure to each stage of the VLSI design flow—from register-transfer level (RTL) design to layout generation (GDSII). Through real-world examples, IPs and open-source toolchains, students will gain valuable experience in design entry, synthesis, placement, routing, timing analysis, and physical verification, making them industry-ready for ASIC design and verification roles.

📊

Beginner
Level

🕐

90
Minutes

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English